IEEE Transactions on Semiconductor Manufacturing

The efficiency of semiconductor frontend manufacturing highly depends on the optimization of resource allocation. In academic works, scheduling methods, i.e., based on Constraint Programming (CP) or Mixed Integer Programming (MIP), are popular tools for solving this optimization problem. As the problem is NP-hard, complete optimization methods do not scale to the problem size and complexity requi…

Research and pilot fabrication lines must plan capacity under highly diversified product portfolios, unstable demand, and frequent recipe changes. We present a prescriptive mixed integer linear programming framework that encodes internal mechanisms of cluster tools, including expected clean time after recipe transitions, finite concurrency at load ports and side buffers under a nonmixing policy, …

Root-cause analysis (RCA) in surface-mount assembly must support rapid containment and verification while remaining auditable under imperfect evidence. We present an uncertainty-aware neurosymbolic pipeline in which a neural evidence layer converts per-board observations into probabilities for defect class, stage-wise mechanism, and parameter risk, and a deterministic semantic layer assembles and…

Multizone pressure chemical mechanical planarization (CMP), which is regarded as irreplaceable in semiconductor manufacturing, is highly dependent on a process control strategy. However, predictive models with strict rules for advanced CMP multizone pressure process control have rarely been examined, even with the development of machine learning applications in semiconductor fabrication. Establis…

Semiconductor manufacturing involves complex multistage processes in which product yield is influenced by intricate interactions among machines, materials, recipes, process durations, queue times, and wafer characteristics, such as warpage. Traditional yield analysis methods typically examine these factors in isolation, overlooking their combined effects. To address this limitation, we propose a …

The precise control of three-dimensional feature profiles during plasma etching is a fundamental challenge in nanoscale device fabrication, directly impacting performance and yield. While conventional physics-based simulations can capture the underlying plasma-surface interactions, their prohibitive computational cost limits their use for large-area analysis or rapid process development. To bridg…

In semiconductor manufacturing, monitoring equipment status is vital in ensuring process stability and efficient equipment operation. Thus, there is an increasing need for a health index that can efficiently reflect the overall condition of the equipment as a unified metric. Previous studies have derived a health index based on real-time time-series data collected from single wafer processing, ov…

Hexagonal silicon oxide defects induced by an ex-situ remote plasma dry etch pre-clean process (SiCoNi<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup>) were observed at the NPN emitter step of a 40 nm BiCMOS device, leading to high defect density and device yield loss. In this work, a systematic investigation was performed to identify the roo…

Accurate temperature monitoring in automated test equipment (ATE) is crucial for ensuring the reliability and quality of semiconductor testing. However, ATE temperature models often rely on noisy, sparsely-sampled sensor data, and existing methods struggle to update models efficiently as operating conditions evolve. This paper presents Neighbor-Pseudo-GP, a probabilistic online method for modelin…

Photovoltaic wafer manufacturing demands near-zero defects, yet anomaly detection models often fail to generalize across manufacturing lines due to domain shift caused by varying imaging devices and process conditions. This letter presents Projection Comparison and Reconstruction (PCR), a framework for cross-domain anomaly detection. Patch-based Domain Fusion mixes source and target images via gr…

As semiconductor manufacturing advances toward the 3 nm node and beyond, wafer sensitivity to particulate and moisture contamination becomes increasingly critical. During front opening unified pod (FOUP) door opening, airflow disturbances and deflection from the equipment front-end module (EFEM) can lead to the intrusion of external moisture and airborne molecular contaminants (AMC), potentially …

Laser grooving is a critical preparatory step in wafer dicing for advanced semiconductor packaging, ensuring reduced mechanical stress and improved dicing precision. However, groove quality assessment remains challenging due to profile irregularities and noise in depth measurement data. This paper presents an automated groove inspection system that leverages long short-term memory (LSTM) networks…

Maintaining a controlled environment is essential for preserving wafer quality and manufacturing yield, as humidity, oxygen, and airborne contaminants can degrade wafer surfaces during fabrication and storage. Computational fluid dynamics (CFD) simulations based on the k–ε turbulence model were applied to reduce relative humidity inside a front opening unified pod (FOUP) using clean dry air (CDA)…

Non-destructive metrology is essential for quality control in semiconductor manufacturing, yet conventional techniques face limitations in characterizing epitaxial silicon-germanium films. This study introduces second harmonic generation (SHG) as a novel approach to address two critical challenges in SiGe process monitoring. First, we demonstrate that SHG can effectively characterize lattice symm…

This study investigates the metal pitch 18 (MP18) via critical dimension (CD) and overlay process window (PW) for a two-metal-layer Ru semi-damascene integration scheme with a fully self-aligned via (FSAV) approach. The via CD and overlay PW was experimentally assessed from electrical tests probing the Kelvin via resistance yield and via-to-line leakage yield under a changing via CD and via y-ove…

Artificial intelligence (AI) and machine learning (ML) demonstrate transformative potential in optimizing complex semiconductor manufacturing. This study addresses two critical areas: process control for 3D NAND fabrication and predictive maintenance (PdM) of fab equipment. For optimizing Thin Film deposition and Chemical Mechanical Planarization (CMP) processes, Artificial Neural Networks (ANNs)…

In semiconductor manufacturing, virtual metrology (VM) leverages high-dimensional sensor data for real-time quality estimation. However, excessive sensor deployment leads to increased operational costs, data redundancy, and system complexity due to substantial infrastructure, installation, and maintenance requirements. To address these manufacturing challenges, we propose a Fast Global Sparse Pri…

Ultrapure water (UPW) is indispensable in semiconductor manufacturing, where it serves as the foundational input for wafer cleaning, chemical dilution, and rinsing steps. As device geometries shrink below 5 nm, even parts-per-trillion (ppt) levels of contaminants can compromise yield, reliability, and compliance with industry standards such as SEMI F63 and ASTM D5127. Emerging contaminants (ECs) …

This paper addresses the incompatible case of parallel batch scheduling, where compatible jobs belong to the same family, and jobs from different families cannot be processed together in the same batch. The state-of-the-art constraint programming (CP) model for this problem relies on specific functions and global constraints only available in a well established commercial CP solver. This paper ex…