dc.title: Dynamic secure DRAM scheduling: porting and extending FlexProf to DDR4 dc.description.abstract: Secure DRAM memory controllers must prevent timing side channels that allow co-resident tenants to infer each other’s memory access patterns. FlexProf achieves this through temporal partitioning, assigning each security domain a fixed, deterministic allocation of DRAM service. However, its design has two limitations. It relies on offline workload profiling to configure per-domain read/write ratios before execution begins, and it was designed and validated for DDR3 timing constraints that do not transfer directly to DDR4 multi-channel environments. This work ports FlexProf from USIMM/DDR3 into Ramulator2 within the CARA-Sim framework and introduces FlexProfDynamic, a redesigned controller that replaces offline profiling with two runtime adaptation mechanisms. The first, Dynamic Read/Write Bias Adjustment (DRWBA), classifies each domain as read phase or write-phase at every pass boundary using write queue depth and asymmetric hysteresis thresholds (enter at depth > 32, exit at depth < 4). The second, Dynamic Turn Allocation (DTA), redistributes DRAM service turns proportionally to observed queue depth, with quantization (right-shift by 3) and per-domain floor/ceiling guar antees that bound any new information leakage introduced by the adaptation signal. All adaptation decisions take effect at pass boundaries, preserving timing determin 5 ism within each pass and limiting side-channel observability to pass granularity rather than per-turn queue state. The DDR4 turn structure is derived formally using Z3 constraint solving against the DDR4-1600K timing specification, producing a 13-cycle uniform turn with ACT slots at c=0 and c=7 and a pinned CAS at c=11. Uniform turn length for both read and write mode closes a pass-duration side channel that would otherwise reveal the read/write mix to an observer timing successive passes. Evaluation across N=1 to N=10 domains shows that FlexProfDynamic out performs FlexProfStatic on four of five workloads at N=2: gzip (+63%), image processing (+167%), linpack (+309%), and pyaes (+224%), by detecting low write queue depth and shifting to near-full read mode without offline profiling. The static controller outperforms the dynamic on the traverse workload (−39%), where its pre-matched write-mode bias requires no adaptation and avoids per-pass rebuild overhead. The evaluation also identifies and characterizes a structural fairness anomaly at even do main counts: the gcd(N,2) transition slot asymmetry causes even-indexed domains to absorb the write-to-read transition penalty twice as often per pass, an unexam ined edge case in the published FlexProf evaluation, which was conducted exclusively at N=7. An empirical cross-run isolation experiment produces a Jensen-Shannon Divergence of 0.0027 bits between a victim domain’s latency distribution under two different attacker workloads. This value is roughly 30 times lower than the intra-run baseline, empirically validating the theoretical isolation claims