Semiconductor Engineering

Multi-GPU traffic modeling; physical neural computing; RISC-V fault injection; automotive CAN timing analysis; EUV source optimization; lithography defect detection; dual-beam EUV efficiency. The post Chip Industry Technical Paper Roundup: June 16 appeared first on Semiconductor Engineering .

Researchers from University of Wisconsin-Madison and AMD Research and Advanced Development published a technical paper titled “Eidola: Modeling Multi-GPU Network Communication Traffic in Distributed AI Workloads.” Abstract: “As distributed AI workloads grow in scale, multi-GPU systems have become essential for training large models. Although techniques like kernel fusion and overlapping communica…

Researchers from the University of Lübeck and TU Hamburg published a technical paper titled “Beyond Silicon: Materials, Mechanisms, and Methods for Physical Neural Computing.” Abstract: “Physical implementations of neural computation now extend far beyond silicon hardware, encompassing substrates such as memristive devices, photonic circuits, mechanical metamaterials, microfluidic networks, chemi…

Chip and system designers scramble to leverage existing and future standards as edge AI increases demand for faster data movement and greater reliability. The post Wi-Fi Flies Higher As Edge AI Build-Out Takes Root appeared first on Semiconductor Engineering .

NAND in space; integrated photonic functions on silicon; light-emitting organic transistor with memory. The post Research Bits: June 15 appeared first on Semiconductor Engineering .

Researchers from Politecnico di Torino and CEA-List published a technical paper titled “InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment.” Abstract “Fault Injection Attacks (FIAs) are a significant threat to hardware security, capable of compromising systems by inducing malicious faults in computation or storage. Evaluating resilience against such attacks is challenging …

Researchers from National Yang Ming Chiao Tung University (NYCU) and Chung Yuan Christian University have published “A Cross-Validated DSPN and Worst-Case Response-Time Framework for Timing Analysis of Automotive CAN Networks”. Abstract “Controller Area Network (CAN) remains a key in-vehicle communication protocol for distributed automotive control systems, where predictable communication timing …

Researchers from The University of Osaka, National Institute for Fusion Science, National Institutes for Quantum Science and Technology, and Osaka Metropolitan University, et al. have published “Optimization of EUV output by experimentally validated radiation-hydrodynamic simulations across a broad laser parameter space”.   Abstract “Practical requirements such as improving wall-plug efficiency a…

Researchers from Hanyang University, Korea University, and Korea Institute of Industrial Technology have published “Failure-Aware Refinement of Vision-Language Model for Lithography Defect Detection”. Abstract “Semiconductor lithography inspection requires reliable detection of small pattern defects such as bridge, burr, pinch, and contamination. In this study, we propose a two-stage vision-langu…

Researchers from Utsunomiya University, RIKEN, The University of Tokyo, and Tohoku University, et al. have published “40% boost in extreme ultraviolet conversion efficiency via simultaneous dual-beam 2-µm laser irradiation”. Abstract “Scaling extreme ultraviolet (EUV) source power for next-generation lithography demands higher conversion efficiency (CE) at reduced per-pulse energies. We demonstra…

2nm; 14A accelerates; memory deal; optimizing EUV output; KGD screening; McKinsey's auto chips report; HW security exploits; humanoids; H-1B policy; diamonds for heat; Europe's IC progress; imec's latest; quantum HW progress towards fault-tolerance. The post Chip Industry Week In Review appeared first on Semiconductor Engineering .

Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory bottlenecks, reduce latency, and boost efficiency. The post Agentic AI Is Changing Data Center Architectures appeared first on Semiconductor Engineering .

It depends on what those models are used, which also can have a big impact on the cost. The post Can AI Create Missing Models? appeared first on Semiconductor Engineering .

Multiphysics analysis for advanced packaging. The post Mastering 3D-IC Verification Complexity appeared first on Semiconductor Engineering .

Reliable performance at higher data rates requires tight coordination between clocking, power delivery, and system-level management. The post Clocked DDR5 Client Memory Modules Enable Scaling To 9600 MT/s For AI PCs appeared first on Semiconductor Engineering .

Packet-based architecture enables out-of-order execution to optimize hardware utilization without retraining the model. The post How To Start Building Edge-Native AI appeared first on Semiconductor Engineering .

Delivering the bandwidth density and efficiency needed to scale AI compute clusters to 1,000 accelerators. The post Building A Production-Ready Optically Connected Rack For AI Scale-Up appeared first on Semiconductor Engineering .

Low-latency fabrics, topology-aware scheduling, and tiered memory bring compute closer to data and reduce coordination overhead. The post Cloud HPC For AI: Addressing Latency, Cost, And Scale At The Architectural Level appeared first on Semiconductor Engineering .

A new architecture enables higher data rates and densities while remaining pin-compatible with traditional DIMM. The post DDR5 MRDIMM: A Transformational Evolution For DDR5 DIMM appeared first on Semiconductor Engineering .

Five architectural domains that are shaped by edge-deployment reality, and how priorities shift across the two primary deployment tiers: edge infrastructure and edge devices. The post Building Edge AI with IP Solutions appeared first on Semiconductor Engineering .