Semiconductor Engineering

Researchers from Université Grenoble Alpes, CNRS, Grenoble INP have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”. Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, and…

Researchers from AMD released “CompPow: A Case for Component-level GPU Power Management”. Abstract “The ever increasing demand for ML-driven intelligence in a wide spectrum of domains has led to ubiquity of GPUs. At the same time, GPUs are notorious for their power consumption needs and often dominate power allocation in a typical ML datacenter. While... » read more The post Improving GPU Energy …

Taiwan, Europe packaging buildout; 2nm ramps; quantum big $; 2 new university hubs; agent honeypots; Samsung strike averted; extreme environment chip design; quantum-dot qubit device fabricated w/high-NA EUV; EU flagship power electronics project; CNTs. The post Chip Industry Week In Review appeared first on Semiconductor Engineering .

A new technical paper, “SHIP: SRAM-Based Huge Inference Pipelines for Fast LLM Serving,” was published by researchers at Nvidia, with work done while at Groq. Abstract “The proliferation of large language models (LLMs) demands inference systems with both low latency and high efficiency at scale. GPU-based serving relies on HBM for model weights and KV... » read more The post Large-scale, SRAM-bas…

Capturing important details without making calculations impractically expensive. The post Beyond Ideal Crystals: The Case For Scale In Atomistic Modeling appeared first on Semiconductor Engineering .

Reduce shallow trench isolation and recess nonuniformity introduced by pattern-dependent etch. The post Process Variation In The Era Of Scaling: Improving Uniformity With Dummy Fill appeared first on Semiconductor Engineering .

Costs can rise with chiplets. Will that change? Will it matter? The post With Chiplets, What Role Does Economics Play? appeared first on Semiconductor Engineering .

More detailed roadmaps are needed to guide how the industry stacks, connects, powers, and cools tomorrow's chips. The post Advancing Heterogeneous Integration Through Industry Roadmap Improvements appeared first on Semiconductor Engineering .

Warpage, heat, and brittleness can cause huge reliability problems for expensive designs. The post Low-Temp Solders Are Suddenly Critical For Chiplets And Photonics appeared first on Semiconductor Engineering .

Sustaining AI progress requires energy-efficient computing with holistic co-design and co-optimization across the entire ecosystem. The post AI & Energy: Bending The Curve appeared first on Semiconductor Engineering .

Deep learning for inspection needs an operationalization layer that puts capability in the hands of engineers closest to the process. The post Enabling Production-Ready AI For Semiconductor Manufacturing appeared first on Semiconductor Engineering .

Enabling electrical and thermal performance enhancements while maintaining the manufacturing efficiency and scalability of the MLF leadframe technology. The post Cost-Effective High-Performance Flip Chip MicroLeadFrame (fcMLF) Package Introduction appeared first on Semiconductor Engineering .

Inspection limits, curvilinear adoption, data volumes, and high-NA EUV are converging to stress the mask ecosystem The post Mask Technology Faces A New Set Of Challenges appeared first on Semiconductor Engineering .

A new technical paper, “Not All Thoughts Need HBM: Semantics-Aware Memory Hierarchy for LLM Reasoning,” was published by researchers at USC and University of Wisconsin-Madison. Abstract “Reasoning LLMs produce thousands of chain-of-thought tokens whose KV cache must reside in scarce GPU HBM. The dominant response — permanently evicting low-importance tokens — is catastrophic for reasoning:... » r…

But figuring out which ones to use, and when to use them, isn't always clear. The post Options Grow For Standardizing Data Movement And Sharing Resources appeared first on Semiconductor Engineering .

Importing functions in PSS; rethinking server architecture; HBM challenges; heterogeneous integration roadmaps; sparse linear algebra. The post Blog Review: May 20 appeared first on Semiconductor Engineering .

Photonics: Programmable PIC; small optical features in hydrogels; on-chip UV generation. The post Research Bits: May 19 appeared first on Semiconductor Engineering .

Micro-transfer printing for silicon photonics; 2D electronics for CFETs; ANN thermal-aware GAA FET modeling; optical phased arrays; ferroelectric tunnel junctions for image generation; functional safety and PPA evaluation. The post Chip Industry Technical Paper Roundup: May 19 appeared first on Semiconductor Engineering .

A new technical paper, “Water-based, large-scale transfer of 2D materials grown on sapphire substrates,” was published by researchers at AMO GmbH, RWTH Aachen University, and AIXTRON SE. Abstract “Two-dimensional materials (2DMs) hold significant potential for future electronics, as demonstrated by high-performing devices for sensing, optics, and electronics. However, scalable growth techniques s…

A new technical paper, “Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors,” was published by researchers at KTH Royal Institute of Technology, Lawrence Livermore National Laboratory, and Barcelona Supercomputing Center. Abstract “The RISC-V Vector Extension~(RVV) is a cornerstone for supporting compute throughout in scientific and machine learning workloads. Yet compiler…