Pre-Silicon Verification and Validation Methodology Targeting Robust RISC-V Chip Designs (BSC)
Technical Paper Link
A new technical paper, “Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL,” was published by researchers at Barcelona Supercomputing Center. Abstract “The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe’s capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, we present a holistic pre-silicon... » read more The post Pre-Silicon Verification and Validation Methodology Targeting Robust R