Rethinking ESD Protection for System-On-Integrated Chiplets (UC Riverside)
Technical Paper Link
A new technical paper, “In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions,” was published by researchers at the University of California, Riverside. Abstract “Heterogeneous integration opens a pathway to three-dimensional chiplet-based microsystem chips. Electrostatic discharge reliability is a major challenge to future smart chips featuring rich functionalities and ultra performance, utilizing advanced heterogeneous... » read more The post Rethinking ESD Prote