This paper presents the development of a CMOS-based pixel readout architecture in a 55 nm HV-CMOS process, targeting the high-hit-density ( > 100 MHz/ cm 2 ) and nanosecond-level timing requirements of the LHCb Upgrade II Upstream Tracker. The architecture is implemented in the COFFEE3 prototype. Each pixel (40 µm × 145 µm) integrates a charge-sensitive amplifier, discriminator, threshold-tuning DAC, a coarse-fine Time-to-Digital Converter (TDC) with fine binning, and timestamp storage, enabled by the fine feature size of the 55 nm node. Dynamic power is reduced by activating the TDC delay line only in hit pixels. Two preamplifier variants are compared via simulation in terms of time-walk and pulse width. Readout dead time is analyzed against the expected hit density. The prototype was functionally tested with laser injection, validating the basic operation of the signal chain and digital packet readout. Since the present chip was fabricated in a standard low-resistivity triple-well process, quantitative sensor-level performance characterization is still ongoing and will be completed with the modified high-resistivity quintuple-well prototypes.