Any digital system on very large scale integrations requires clock distributions. For the realization, a dedicated clock tree or a mesh clock is frequently used. Field programmable gate arrays have numerous general-purpose programmable wires based on switching matrices to connect the outputs and inputs of look-up tables and input/output ports. However, field programmable gate arrays never use numerous general-purpose programmable wires for their clock distributions as well as other very large scale integrations to satisfy with the clock skew margin. Field programmable gate arrays also take the dedicated clock trees although the programmability is not high. Currently, field programmable gate arrays can support multiple dedicated clock routing or multiple clock trees. However the number of clock trees is fixed and limited to a small number. Even if application requires a lot of clock distributions, the clock distribution cannot be supported in current field programmable gate arrays. Therefore, this paper proposes a more flexible clock distribution method using general-purpose programmable wires based on wiring channels and switching matrices. In addition, to solve clock skew increase problem, we have introduced a new flip-flop with a two-phase clock signal. This paper presents the simulation results of the proposed clock distribution method on an originally designed filed programmable gate array. In addition, this paper also presents the experimental results that the proposed clock distribution method can work correctly on a Cyclone V field programmable gate array.