Programmable clock distribution using switching matrices for field programmable gate arrays

Any digital system on very large scale integrations requires clock distributions. For the realization, a dedicated clock tree or a mesh clock is frequently used. Field programmable gate arrays have numerous general-purpose programmable wires based on switching matrices to connect the outputs and inputs of look-up tables and input/output ports. However, field programmable gate arrays never use numerous general-purpose programmable wires for their clock distributions as well as other very large sc