Modified spike backpropagation design towards highly parallelable hardware implementation

This work presents a hardware-algorithm co-designed framework for neuromorphic computing, enabling efficient supervised learning in spike-based neural architectures. First, synaptic updates are reformulated as low-rank outer products of forward spike vectors and backward error gradients via singular value decomposition (SVD), enabling direct parallelization on 1T1R arrays. Second, a stochastic computing scheme replaces conventional sequential updates with probabilistic pulse-driven modulation, a