The series-connection of silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) is essential for extending the blocking voltage capability in high-power applications, yet it inevitably suffers from dynamic voltage imbalance during switching transients. Dynamic voltage imbalance originates mainly from discrepancies in device intrinsic parasitic parameters as well as in circuit parasitic parameters, including stray inductances in the power loop and parasitic capacitances to ground. Passive balancing techniques incur additional energy dissipation, while most active strategies suffer from limited response speed or introduce excessive gate capacitance that degrades switching performance. To address these issues, this article proposes a novel adaptive gate delay control (AGDC) method. The proposed technique features a simple circuit that converts the slew rate of the drain-source voltage (vds) into a square-wave signal, from which a time difference is extracted by a field-programmable gate array (FPGA) for adaptive iterative adjustment. Experimental comparisons with conventional gate drive (CGD) and with an existing active scheme confirm the method’s effectiveness in achieving active voltage balancing without compromising the inherent switching speed of the devices.